1. Field of the Invention
This invention relates to a process for manufacturing a semiconductor integrated circuit device comprising a bipolar transistor formed on a semiconductor substrate and a complementary field-effect transistor (hereinafter, referred to as CMOS).
2. Description of the Related Art
BiCMOS technology is one for forming a bipolar transistor having characteristics of high-speed actuation and high driving performance and a CMOS having a characteristic of low power consumption, on the same substrate, which is one of the most effective procedures for meeting recent demands on lower power consumption and higher speed in a semiconductor device.
Since BiCMOS technology requires many steps, cost reduction has been strongly desired. JP-A 4-74434 and JP-A 8-55924 have disclosed techniques for meeting such demands.
As the first prior art, description of JP-A 4-74434 will be briefly illustrated by referring to FIGS. 5(a) to (c) and FIGS. 6(a) to (c).
As seen in FIG. 5(a), on a P type silicon substrate 301 are formed an N.sup.+ buried layer 303 and a P.sup.+ buried layer 302; is grown an N type epitaxial layer 304; and then are formed an N well 305 and a P well 306.
Then, on the substrate are formed a field oxide film 307 by LOCOS technique and then a gate oxide film 308, and boron ion is implanted with a mask 901 to form a P type base area 309.
Then, as seen in FIG. 5(b), an emitter contact 310 and a collector contact 311 are opened with a mask 902.
As seen in FIG. 5(c), a polysilicon 312 is deposited over the whole surface, and then arsenic ion is implanted on a given area.
Then, as seen FIG. 6(a), phosphorous ion is implanted in a given area with a mask 903.
Then, as seen FIG. 6(b), the polysilicon 312 is selectively etched to form an emitter polysilicon 314, a collector polysilicon 315 and a gate polysilicon 313.
Herein, the arsenic ion is implanted for forming an emitter diffusion layer 317 which will be described later, while the phosphorous ion is implanted for forming a collector diffusion layer 318 and an N.sup.+ type gate polysilicon 313 both of which will be described later.
Then, as seen in FIG. 6(c), an N type LDD layer 320 and a P type LDD layer 321 are formed; an oxide film is deposited over the whole area of the wafer, and it was etched back by RIE technique to form a side wall 319 consisting of an oxide film.
Then, an N.sup.+ type source-drain 322 is formed, and a P.sup.+ type source-drain 323 and a extrinsic base 316 are simultaneously formed.
Then, the substrate is treated by heat to form an emitter diffusion layer 317 and a collector diffusion layer 318, to give a device portion of a BiCMOS integrated circuit.
Next, as the second prior art, the technique described in JP-A 8-55924 will be briefly described by referring to FIGS. 7(a) to (c) and FIGS. 8(a) to (c).
As seen in FIG. 7(a), on a P type silicon substrate 401 are formed an N.sup.+ buried layer 403, a P.sup.+ buried layer 402, an N well 406 and a P well 405, and then boron ion is implanted through a first oxide film 404 about 30 nm thick, using a mask 911. The conditions of ion-implantation may be, for example, 7.0.times.10.sup.13 cm.sup.-2 at 10 keV. Thus, a P type base area 409 is formed.
As seen in FIG. 7(b), after removing the first oxide film 404, a gate oxide film 408 10 nm thick is formed by thermal oxidation. Then, a part of the gate oxide film 408 for an emitter contact 410 is removed with a mask 912 by, for example, selectively etching with 10% HF for 10 seconds.
Then, as seen in FIG. 7(c), a polysilicon 412 about 350 nm thick is deposited over the whole area of the wafer by LPCVD technique, and then boron ion is implanted in an area where a gate of PMOS will be formed, with a mask 913, for example, under the conditions of 2.times.10.sup.15 cm.sup.-2 at 20 keV.
Then, as seen in FIG. 8(a), arsenic ion or phosphorous ion is implanted on the areas where an emitter and a gate of NMOS will be formed; for example, under the conditions of 1.times.10.sup.16 cm.sup.-2 at 100 keV for arsine.
Then, as seen FIG. 8(b), the polysilicon 412 is selectively etched to form an emitter polysilicon electrode 414 and a gate polysilicon electrode 413.
Then, as seen in FIG. 8(c), an N type LDD layer 420 and a P type LDD layer 421 are formed, and a dielectric film is deposited over the whole area of the wafer, and etched back to form a side wall 419 which consists of an oxide film, preferably of an oxide film and a nitride film on the oxide film.
Then, an N.sup.+ type source-drain 422 is formed, and a P.sup.+ type source-drain 423 and a extrinsic base 416 are simultaneously formed, and the substrate is treated by heat.
Herein, the gate of the PMOS is doped by an ion-implantation of a P.sup.+ type source-drain 423, and the gate of the NMOS is doped by an ion-implantation of a N.sup.+ type source-drain 422.
After above process, silicification may be conducted on the surfaces of the gate polysilicon electrode 413, the P.sup.+ type source-drain 423, N.sup.+ type source-drain 422 and/or the emitter polysilicon electrode 414 by a known technique.